As a present-day semiconductor memory of large capacity, a DRAM is most popular, and is extensively used in e.g., a computer system. As a non-volatile semiconductor memory, on the other hand, a flash memory is extensively used. However, the DRAMs or the flash memories, which now are mainstream devices, are said to be reaching the limit of miniaturization in several years to come. Hence, investigations into a variety of large-capacity semiconductor memory devices, capable of replacing the DRAMs or flash memories, are now going on. In particular, variable resistance memories or resistive switching memories that exploit the phenomenon in which changes in resistance are produced by applying a voltage to transition metal oxides, such as perovskite oxides or NiO, are stirring up notice. Examples of these semiconductor memory devices include RRAMs or ReRAMs. The variable resistance memories, in which the variable resistance states may be maintained even after power down, may operate as volatile memories. These variable resistance memories or resistive switching memories are disclosed in Non-Patent Documents 1 and 2.
FIG. 4A shows an example configuration of a memory cell 40 of the variable resistance memory. This memory cell 40 includes a variable resistance element 41 and a cell transistor 42 connected in series between a bit line 31 and a source line 33. A resistance value may be written in the variable resistance element 41 by way of programming. The resistance value may be read out by allowing the current to flow through the variable resistance element 41.
FIG. 4B shows an example inner configuration of the variable resistance element 41. The variable resistance element includes a first electrode 45, connected to the bit line 31, a second electrode 46, connected to a cell transistor, not shown, and an insulation film 47, sandwiched between the first and second electrodes 45, 46. It is reported that, in case a transition metal oxide is used for the insulation film 47, a wide variety of characteristics may be exhibited depending on the combination of substances used for the first and second electrodes 45, 46.
In writing (programming) data in the variable resistance element, two different sorts of write are needed. One is the write of changing the high resistance state (sometimes referred to below as Register to ReSet or RRST) to the low resistance state (sometimes referred to below as Register to SeT or RSET). The other is the write of changing the low resistance state (RSET) to the high resistance state (PRST). In the description to follow, the write for changing the high resistance state (PRST) to the low resistance state (RSET) is also referred to as SET write or Set, and the write for changing the low resistance state to the high resistance state is also referred to as RESET write or Reset.
The operation of SET write or the RESET write may be classified into a unipolar operation and a bipolar operation. In the unipolar operation, the write is performed as the voltage is applied to the variable resistance element in the same direction for Set and Reset. In the bipolar operation, the write is performed as the voltage is applied to the variable resistance element in the opposite directions for Set and Reset. The bipolar write operation will now be described with reference to FIG. 4C, in which the voltage applied across the electrodes of the variable resistance element is plotted on the abscissa and the value of the current flowing between both ends at this time is plotted on the ordinate. It is assumed that the variable resistance element is initially in the reset state. This state is the high resistance state. If, in this reset state, positive voltage VDSET is applied across both terminals of the variable resistance element (point A in FIG. 4C), the variable resistance element is set to the low resistance state from the high resistance state (transition from point A to point B in FIG. 4C). The maximum current flowing at this time is labeled ICOMP.
If conversely the write is from the Set state to the Reset state, the voltage is applied in the reverse direction to that to the Set state. That is, a voltage VDRST is applied to the variable resistance element in an opposite direction to that for Set (point C in FIG. 4C). The current flowing at this time is labeled IRST. This resets the variable resistance element from the Set state so that the resistance element reverts to the large resistance state (transition from a point C to a point D in FIG. 4C). In reading out from the resistance element, a voltage lower than VDSET is applied to the resistance element to check the current flowing at such time to verify whether the resistance element is in the Set state or in the Reset state.
In the Non-Patent Documents 1, 2, it is stated that, in a memory that uses a variable resistance element as a storage element, the resistance value after SET write (resistance value of RSET) depends on the maximum current value used at the write time. In the Non-Patent Documents 3, 4, it is stated that variations in Vth (threshold value voltage) of a MOS transistor depend on the channel area, although the statement is not directly relevant to the semiconductor device that uses the variable resistance element as memory element. The Non-Patent Documents 3, be referred to in the description of exemplary embodiments of the present invention.
The Non-Patent Document 5 shows a variable resistance memory having a memory cell arrangement in which a MOS transistor is connected in series with a variable resistance element. The Non-Patent Documents 1 and 2 show a memory that uses a variable resistance element (variable element memory or resistance switching memory). The variable element memory distinguishes between states 0 and 1, depending on resistance values, so as to be used as memory. Patent Document 1 shows that the memory is the above mentioned bipolar memory which controls write-0 as a preset current is allowed to flow in a first direction through the variable resistance element while controlling write-1 as a preset current is allowed to flow in a second direction opposite to the first direction through the variable resistance element.    [Patent Document 1]    JP Patent Kokai Publication No. JP2009-170006A, which corresponds to U.S. Pat. No. 8,009,456B2 and US2011/002157A1    [Patent Document 2]    JP Patent Kokai Publication No. JP2011-65737A, which corresponds to US2011/069533A1    [Non-Patent Document 1]    U. Russo et al., ‘Study of Multilevel Programming in Programmable Metallization Cell (PMC) Memory’, IEEE TRANSACTIONS ON ELECTRON DEVICES VOL. 56, No. 5, P 1040-1047, 2009    [Non-Patent Document 2]    H. Y. Lee et al., ‘Low Power and High Speed Bipolar Switching with A Thin Reactive Ti Buffer Layer in Robust HfO2 Based PRAM’, international electron Device meeting 2008 (IEDM 2008), P 297-300    [Non-Patent Document 3]    Tomohisa MIZUNO, ‘Physics of transistor characteristic fluctuations’, Applied Physics vol. 75 No. 9 P 1103-1108, 2009    [Non-Patent Document 4]    Kenji TANIGUCHI, ‘Introduction to CMOS Analog Circuit’, P 146, CQ Publications    [Non-Patent Document 5]    W. W. Zhuang et al., ‘Novel Colossal Magnetoresistive Thin Film Nonvolatile Resistance Random Access Memory (PRAM)’, 2002, 12, pp 193-196